This application claims the benefit of priority to Swedish Application No. 9804529-7, filed on Dec. 23, 1998, entitled, Flexible Memory Channel, which is incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates generally to memory channel means, and more particularly to memory channel means comprising several memory channels transferring data streams between different blocks and an internal memory means on a data chip.
2. Description of the Prior Art
General purpose and special purpose chips comprise many different blocks such as a CPU, control circuits, I/O-ports, memory units, registers etc., exchanging data, usually by means of an internal bus. A bus is a set of connectors designed to transfer data either unidirectionally or bidirectionally. Some buses are dedicated buses, i.e. buses having a unique source and destination. Thus, if n blocks have to be interconnected by buses in all possible ways, n(nxe2x88x921) dedicated buses are required. Generally, bus drivers and logic circuits are required to control the buses. These designs involve considerable costs, and therefore buses which can connect one of several sources to one of several destinations are used. However, this design with fewer buses requires more complex logic circuits and bus controllers.
Traditional buses are classified as CPU-memory buses or I/O buses. I/O buses may be lengthy and interconnect many types of devices, having a wide range in the data bandwidth of the devices. On the other hand CPU-memory buses are short, high speed buses and designed to maximize CPU-memory bandwidth. Also single buses for both memory and I/O devices are available.
DCAM(trademark)-101 from LSI Logic Corporation is a special purpose chip for digital still cameras. It contains different functions needed to preview, capture, compress, filter, store, transfer and display digital images. Consequently, the DCAM(trademark)-101 chip comprises several blocks and units, such as a CPU, memory units, different I/O interfaces, and control blocks etc., all of which exchange data through a traditional internal bus.
Such a traditional bus enables only passive transmission of data between different blocks on the chip, i.e. the data is not manipulated in any way during the transfer.
The main object of the present invention is to provide an improved memory channel means in order to move data streams between different blocks on a chip and simultaneously manipulate the data being transferred.
Another object of the invention is to change the order of the data within the data streams.
A further object of the invention is to provide an improved memory channel means, which reduces the required memory capacity on the chip.
Still another object of the invention is to obtain regular addressing schemes.
An additional object of the invention is to provide memory channels and address generators operating in parallel and accessing the memory independent of each other.
These and other objects, features and advantages of the invention are accomplished by a flexible memory channel means according to the invention, comprising several memory channels, each channel having source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory, and will be apparent from the following detailed description in conjunction with the drawings.